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document order number: mm908e626 rev. 8.0, 4/2012 freescale semiconductor ? technical data * this document contains certain information on a new product. ? specifications and information herein are subject to change without notice. ? freescale semiconductor, inc. , 2005-2012. all rights reserved. integrated stepper motor driver with embedded mcu and lin serial communication the 908e626 is an integrated singl e package solution that includes a high performance hc08 microcontroller with a smartmos analog control ic. the hc08 includes flash memory, a timer, enhanced serial communications interface (esci), an analog-to-digital converter (adc), internal serial peripheral interface (spi), and an internal clock generator (icg) module. the anal og control die provides fully protected h-bridge outputs, volta ge regulator, autonomous watchdog, and local interconnect network (lin) physical layer. the single package solution, togethe r with lin, provides optimal application performance adjustments and space-saving pcb design. it is well-suited for the control of automotive stepper applications like climate control and light-leveling. features ? high performance m68hc08ey16 core ?16 kb of on-chip flash memory ?512 b of ram ? internal clock generation module ? two 16-bit, two-channel timers ? 10-bit analog-to-digital converter ? four low r ds(on) half-bridge outputs ? 13 microcontroller i/os 908e626 figure 1. 908e626 simplified application diagram 908e626 stepper motor driver with embedded mcu and lin ek suffix (pb-free) 98arl10519d 54-pin soicw-ep ordering information device (add an r2 suffix for tape and reel orders) temperature range (t a ) package MM908E626AVPEK -40 to 115 c 54 soicw ep lin vrefh vdda evdd vdd vrefl vssa rst a rst irq a irq evss vss ss ptb1/ad1 rxd pte1/rxd ptd1/tach1 fgen bemf ptd0/tach0/bemf hb1 hb2 hb3 hb4 hvdd porta i/os portb i/os gnd[1:2] ep vsp1:3] microcontroller ports switchable internal v dd output portc i/os bipolar n s step motor
analog integrated circuit device data ? 2 freescale semiconductor 908e626 figure 2. figure 1. 908e626 si mplified internal block diagram irq ptb6/ad6/tbch0 rst vrefl vssa evss evdd vdda vrefh ptb7/ad7/tbch1 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb0/ad0 pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 ptc4/osc1 ptc3/osc2 ptc2/mclk flsvpp pta5/spsck ptc1/mosi ptc0/miso pte0/txd ptd1/tach1 ptd0/tach0 ptb1/ad1 pte1/rxd voltage regulator spi & control reset control module autonomous watchdog lin physical layer analog multiplexer half bridge driver & diagnostic switched vdd driver & diagnostic vss vdd hvdd hb1 hb2 hb3 hb4 irq_a rst_a ss bemf fgen vsup1-3 gnd1-2 lin adout txd spsck mosi miso rxd chip temp vsup prescaler interrupt control module vsup vsup vsup vsup fgen ss bemf analog die mcu die m68hc08 cpu alu port b ddrb ptb0/ad0 cpu registers ddre port e pte1/rxd pte0/txd ptb0/ad0 ptb2/ad2 ptb3/ad3 ptb4/ad4 ptb5/ad5 ptb6/ad6/tbch0 ptb7/ad7/tbch1 ddrd port d ptd1/tach1 ptd0/tach0 port c ddrc ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso bemf module prescaler module arbiter module periodic wake-up timebase module configuration register module serial peripheral interface module computer operating properly module enhanced serial communication interface module 2-channel timer interface module b 2-channel timer interface module a 5-bit keyboard interrupt module single breakpoint break module ddra port a pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 pta5/spsck pta6/ss security module power-on reset module power vss vdd 10 bit analog-to- digital converter module vssa vrefl vdda vrefh single external irq module irq 24 integral system integration module rst internal clock generator module osc1 osc2 user flash vector space, 36 bytes flash programming (burn-in), 1024 bytes monitor rom, 310 bytes user ram, 512 bytes user flash, 15,872 bytes control and status register, 64 bytes internal bus half bridge driver & diagnostic half bridge driver & diagnostic half bridge driver & diagnostic bemf bemf bemf fgen fgen fgen
analog integrated circuit device data ? freescale semiconductor 3 908e626 pin connections pin connections figure 3. 908e626 pin connections table 1. 908e626 pi n definitions a functional description of each pin can be found in the functional pin description section beginning on page 15 . die pin pin name formal name definition mcu 1 2 6 7 8 11 ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptb5/ad5 ptb4/ad4 ptb3/ad3 ptb1/ad1 port b i/os these pins are special function, bi directional i/o port pins that are shared with other functi onal modules in the mcu. mcu 3 4 5 ptc4/osc1 ptc3/osc2 ptc2/mclk port c i/os these pins are special function, bi directional i/o port pins that are shared with other functi onal modules in the mcu. mcu 9 irq external interrupt input this pin is an asynchronous external interrupt input pin. mcu 10 rst external reset this pin is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. mcu 12 13 ptd0/tach0/bemf ptd1/tach1 port d i /os these pins are special function, bidirectional i /o port pins that are shared with other functi onal modules in the mcu. pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 vrefh vdda evdd evss vssa vrefl pte1/rxd rxd vss nc vdd nc nc nc hvdd nc hb4 vsup3 gnd2 hb3 nc flsvpp ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 irq rst ptb1/ad1 ptd0/tach0/bemf ptd1/tach1 nc fgen bemf rst_a irq_a ss lin nc nc hb1 vsup1 gnd1 hb2 vsup2 1 11 12 13 14 15 16 17 18 19 20 9 10 21 22 23 24 25 26 27 6 7 8 4 5 2 3 54 44 43 42 41 40 39 38 37 36 35 46 45 34 33 32 31 30 29 28 49 48 47 51 50 53 52 exposed pad transparent top view of package
analog integrated circuit device data ? 4 freescale semiconductor 908e626 pin connections ? 14, 21, 22, 28, 33, 35, 36, 37, 39 nc no connect not connected. mcu 42 pte1/ rxd port e i /o this pin is a special f unction, bidirectional i/o port pin that can is shared with other functi onal modules in the mcu. mcu 43 48 vrefl vrefh adc references these pins are the reference voltage pins for the analog-to-digital converter (adc). mcu 44 47 vssa vdda adc supply pins these pins are the power supply pins for the analog-to-digital converter. mcu 45 46 evss evdd mcu power supply pins these pins are the ground and power supply pins, respectively. the mcu operates from a single power supply. mcu 49 50 52 53 54 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 port a i /os these pins are special function, bi directional i/o port pins that are shared with other functi onal modules in the mcu. mcu 51 flsvpp test pin for test purposes only. do not connect in the application. analog 15 fgen current limitation frequency input this is the input pin for the half-bridge current limitation pwm frequency. analog 16 bemf back electromagnetic force output this pin gives the user informat ion about back electromagnetic force (bemf). analog 17 rst_a internal reset this pin is the bidirectional reset pin of the analog die. analog 18 irq_a internal interrupt output this pin is the interrupt output pi n of the analog die indicating errors or wake-up events. analog 19 ss slave select this pin is the spi slave select pin for the analog chip. analog 20 lin lin bus this pin represents the single-wi re bus transmitter and receiver. analog 23 26 29 32 hb1 hb2 hb3 hb4 half-bridge outputs this device includes power mosfets configured as four half-bridge driver outputs. these outputs may be configured for step motor drivers, dc motor drivers, or as high side and low side switches. analog 24 27 31 vsup1 vsup2 vsup3 power supply pins these pins are device power supply pins. analog 25 30 gnd1 gnd2 power ground pins these pins are device power ground connections. analog 34 hvdd switchable v dd output this pin is a switchable v dd output for driving resistive loads requiring a regulated 5.0 v supply; e.g., 3 pin hall-effect sensors. analog 38 vdd voltage regulator output the 5.0 v voltage regulator output pin is intended to supply the embedded microcontroller. analog 40 vss voltage regulator ground ground pin for the connection of all non-power ground connections (microcontroller and sensors). analog 41 rxd lin transceiver output this pin is the output of lin transceiver. ? ep exposed pad exposed pad the exposed pad pin on the bottom side of the package conducts heat from the chip to the pcb board. table 1. 908e626 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 15 . die pin pin name formal name definition
analog integrated circuit device data ? freescale semiconductor 5 908e626 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground un less otherwise noted. exceeding limits on any pin may cause permanent damage to the device. rating symbol value unit electrical ratings supply voltage analog chip supply voltage under normal operation (steady- state) analog chip supply voltage under transient conditions (1) microcontroller chip supply voltage v sup( ss ) v sup( pk ) v dd - 0.3 to 28 - 0.3 to 40 - 0.3 to 6.0 v input pin voltage analog chip microcontroller chip v in (analog) v in (mcu) - 0.3 to 5.5 v ss - 0.3 to v dd + 0.3 v maximum microcontroller current per pin all pins except vdd, vss, pta0 : pta6, ptc0 : ptc1 pins pta0 : pta6, ptc0 : ptc1 i pin (1) i pin (2) 15 25 ma maximum microcontroller v ss output current i mvss 100 ma maximum microcontroller v dd input current i mvdd 100 ma lin supply voltage normal operation (steady-state) transient conditions (1) v bus(ss) v bus(dynamic) -18 to 28 40 v esd voltage human body model (2) machine model (3) charge device model (4) v esd1 v esd2 v esd3 3000 150 500 v notes 1. transient capability for pulses with a time of t < 0.5 sec. 2. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 3. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 4. esd3 testing is performed in accordanc e with charge device model, robotic (c zap = 4.0 pf).
analog integrated circuit device data ? 6 freescale semiconductor 908e626 electrical characteristics maximum ratings thermal ratings storage temperature t stg - 40 to 150 ? c operating case temperature (5) t c - 40 to 115 ? c operating junction temperature (6) t j - 40 to 135 ? c peak package reflow temperature during solder mounting (7)(8) t pprt note 8 ? c notes 5. the limiting factor is junction temperat ure, taking into account the power dissipat ion, thermal resistance, and heat sinking. 6. the temperature of analog and mcu die is strongly linked via t he package, but can differ in dy namic load conditions, usually because of higher power dissipation on the analog die. the analog die temperature must not exceed 150 c under these conditions 7. pin soldering temperature is for 10 seconds maximum duration. not designed for immersion solder ing. exceeding these limits ma y cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability meets pb-free requirem ents for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.frees cale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i .e. mc33xxxd enter 33xxx), and review parametrics. table 2. maximum ratings all voltages are with respect to ground un less otherwise noted. exceeding limits on any pin may cause permanent damage to the device. rating symbol value unit
analog integrated circuit device data ? freescale semiconductor 7 908e626 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electrical characteristics all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v ? v sup ? 16 v, -40 ? c ? t j ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 ? c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit supply voltage nominal operating voltage v sup 8.0 ? 18 v supply current normal mode v sup = 12 v, power die on (pson = 1), mcu operating using internal oscillator at 32 mhz (8.0 mhz bus frequency), spi, esci, adc enabled stop mode (9) v sup = 12 v, cyclic wake-up disabled i run i stop ? ? 20 ? ? 75 ma ? a digital interface ratings (analog die) output pins rst_a , irq_a low state output voltage (i out = - 1.5 ma) high state output voltage (i out = 1.0 ? a) v ol v oh ? 3.85 ? ? 0.4 ? v output pins bemf, rxd low state output voltage (i out = - 1.5 ma) high state output voltage (i out = 1.5 ma) v ol v oh ? 3.85 ? ? 0.4 ? v output pin rxd ? capacitance (10) c in ?4.0?pf input pins rst_a , fgen, ss input logic low voltage input logic high voltage v il v ih ? 3.5 ? ? 1.5 ? v input pins rst_a , fgen, ss ? capacitance (10) c in ?4.0?pf pins rst_a , irq_a ? pull-up resistor r pullup 1 ?10?k ? pin ss ? pull-up resistor r pullup 2 ?60?k ? pins fgen, mosi, spsck ? pull-down resistor r pulldown ?60?k ? pin txd ? pull-up current source i pullup ?35? ? a notes 9. stop mode current will increase if v sup exceeds 15 v. 10. this parameter is guaranteed by process monitoring but is not production tested.
analog integrated circuit device data ? 8 freescale semiconductor 908e626 electrical characteristics static electrical characteristics system resets and interrupts high voltage reset threshold hysteresis v hvron v hvrh 27 ? 30 1.5 33 ? v low voltage reset threshold hysteresis v lvron v lvrh 3.6 ? 4.0 100 4.7 ? v mv high voltage interrupt threshold hysteresis v hvion v hvih 17.5 ? 21 1.0 23 ? v low voltage interrupt threshold hysteresis v lvion v lvih 6.5 ? ? 0.4 8.0 ? v high temperature reset (12) threshold hysteresis t ron t rh ? 5.0 170 ? ? ? ? c high temperature interrupt (13) threshold hysteresis t ion t ih ? 5.0 160 ? ? ? ? c voltage regulator normal mode output voltage i out = 60 ma, 6.0 v < v sup < 18 v v ddrun 4.75 5.0 5.25 v load regulation i out = 80 ma, v sup = 9.0 v v lr ? ? 100 mv stop mode output voltage (maximum output current 100 ? a) (11) v ddstop 4.45 4.7 5.0 v notes 11. tested to be vlvron < vddstop 12. this parameter is guaranteed by process monitoring but is not production tested. 13. high temperature interrupt (hti) threshold is linked to high temperature reset (htr) threshold (htr = hti + 10 ? c). table 3. static electric al characteristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v ? v sup ? 16 v, -40 ? c ? t j ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 ? c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 9 908e626 electrical characteristics static electrical characteristics lin physical layer output low level txd low, 500 ? pull-up to v sup v lin-low ??1.4 v output high level txd high, i out = 1.0 ? a v lin-high v sup - 1.0 ? ? v pull-up resistor to v sup r slave 20 30 60 k ? leakage current to gnd recessive state (- 0.5 v < v lin < v sup ) i bus_pas_ rec 0.0 ? 20 ? a leakage current to gnd (v sup disconnected) including internal pull-up resistor, v lin @ -18 v including internal pull-up resistor, v lin @ +18 v i bus_no_gnd i bus ? ? - 600 25 ? ? ? a lin receiver recessive dominant threshold input hysteresis v ih v il v ith v ihy 0.6v lin 0 ? 0.01v sup ? ? v sup / 2 ? v sup 0.4v lin ? 0.1v sup v lin wake-up threshold v wth ?v sup / 2 ? v half-bridge outputs (hb1 : hb4) switch on resistance @ t j = 25 ? c with i load = 1.0 a high side low side r ds(on)hb_hs r ds(on)hb_ls ? ? 425 400 500 500 m ? high side over-current shutdown i hbhsoc 3.0 ? 7.5 a low side over-current shutdown i hblsoc 2.5 ? 7.5 a low side current limitation @ t j = 25 ? c current limit 1 (cls2 = 0, cls1 = 1, cls0 = 1) current limit 2 (cls2 = 1, cls1 = 0, cls0 = 0) current limit 3 (cls2 = 1, cls1 = 0, cls0 = 1) current limit 4 (cls2 = 1, cls1 = 1, cls0 = 0) current limit 5 (cls2 = 1, cls1 = 1, cls0 = 1) i cl1 i cl2 i cl3 i cl4 i cl5 ? 210 300 450 600 55 260 370 550 740 ? 315 440 650 880 ma half-bridge output high threshold for bemf detection v bemfh ?- 300.0v half-bridge output low threshold for bemf detection v bemfl ? - 60 - 5.0 mv hysteresis for bemf detection v bemfhy ?30?mv low side current-to-voltage ratio (v adout [v] / i hb [a]) csa = 1 csa = 0 ratio h ratio l 7.0 1.0 12.0 2.0 14.0 3.0 v/a table 3. static electric al characteristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v ? v sup ? 16 v, -40 ? c ? t j ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 ? c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? 10 freescale semiconductor 908e626 electrical characteristics static electrical characteristics switchable v dd output (hvdd) over-current shutdown threshold i hvddoct 24 30 40 ma v sup down-scaler voltage ratio (ratio vsup = v sup / v adout )ratio vsup 4.8 5.1 5.35 ? internal die temperature sensor voltage / temperature slope s ttov ?19?mv/ c output voltage @ 25 c v t25 1.7 2.1 2.5 v table 3. static electric al characteristics (continued) all characteristics are for the analog chip only. refer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteristics noted under conditions 9.0 v ? v sup ? 16 v, -40 ? c ? t j ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 ? c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 11 908e626 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics microcontroller parametrics table 4. dynamic electrical characteristics all characteristics are for the analog chip only. please re fer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characterist ics noted under conditions 9.0 v ? v sup ? 16 v, -40 ? c ? t j ? 135 ? c, unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 ? c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit lin physical layer propagation delay (14) , (15) txd low to lin low txd high to lin high lin low to rxd low lin high to rxd high txd symmetry rxd symmetry t txd -lin-low t txd-lin-high t lin-rxd-low t lin-rxd-high t txd-sym t rxd-sym ? ? ? ? - 2.0 - 2.0 ? ? 4.0 4.0 ? ? 6.0 6.0 8.0 8.0 2.0 2.0 ? s output falling edge slew rate (14) , (16) 80% to 20% sr f -1.0 - 2.0 - 3.0 v/ ? s output rising edge slew rate (14) , (16) 20% to 80%, r bus > 1.0 k ? , c bus < 10 nf sr r 1.0 2.0 3.0 v/ ? s lin rise / fall slew rate symmetry (14) , (16) sr s - 2.0 ? 2.0 ? s autonomous watchdog (awd) awd oscillator period t osc ?40? ? s awd period low = 512 t osc tj < 25 c tj ? 25 c t awdph 16 16 27 22 34 28 ms awd period high = 256 t osc tj < 25 c tj ? 25 c t awdpl 8.0 8.0 13.5 11 17 14 ms awd cyclic wake-up on time t awdhpon ?90? ? s notes 14. all lin characteristics are for initial lin slew rate selection (20 kbaud) (srs0 : srs1= 00). 15. see figure 4 , page 12 . 16. see figure 5 , page 13 . table 5. microcontroller for a detailed microcontroller description, refer to the mc68hc908ey16 datasheet. module description core high performance hc08 core with a maximum internal bus frequency of 8.0 mhz timer two 16-bit timers with two channels (tim a and tim b) flash 16 k bytes ram 512 bytes
analog integrated circuit device data ? 12 freescale semiconductor 908e626 electrical characteristics timing diagrams timing diagrams figure 4. lin timing description adc 10 bit analog-to-digital converter spi spi module esci standard serial communication interface (sci) module ? bit-time measurement ? arbitration ? prescaler with fine baud rate adjustment icg internal clock generation module bemf counter special counter for smartmos bemf output table 5. microcontroller for a detailed microcontroller description, refer to the mc68hc908ey16 datasheet. module description tx rx lin recessive state recessive state dominant state 0.9 vsup 0.4 vsup 0.6 vsup 0.1 vsup t tx-lin-low t tx-lin-high t lin-rx-low t lin-rx-high t txd-lin-low t txd-lin-high txd rxd 0.3 v lin txd lin 0.9 v sup 0.1 v sup 0.7 v lin t lin-rxd-high t lin-rxd-low
analog integrated circuit device data ? freescale semiconductor 13 908e626 electrical characteristics functional diagrams figure 5. lin slew rate description functional diagrams figure 6. free wheel diode forward voltage sr f = dominant state 0.8 vsup 0.2 vsup 0.8 vsup 0.2 vsup ? t fall-time ? t rise-time ? v fall ? v rise ? v fall ? t fall-time sr r = ? v rise ? t rise-time 0.8 v sup 0.2 v sup 0.2 v sup 0.8 v sup 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 amperes volts h-bridge low side t j = 25c amperes volts
analog integrated circuit device data ? 14 freescale semiconductor 908e626 electrical characteristics functional diagrams figure 7. dropout voltage on hvdd 0 50 100 150 200 250 0 5 10 15 20 25 i load (ma) drop out (mv) t a = 125c t a = 25c t a = -40c dropout (mv) i load (ma) 5.0
analog integrated circuit device data ? freescale semiconductor 15 908e626 functional description introduction functional description introduction the 908e626 device was designed and developed as a highly integrated and cost-eff ective solution for automotive and industrial applications. for automotive body electronics, the 908e626 is well suited to perform stepper motor control, e.g. for climate or light-levelli ng control via a 3-wire lin bus. this device combines an standard hc08 mcu core (68hc908ey16) with flash memory together with a smartmos ic chip. the smartmos ic chip combines power and control in one chip . power switches are provided on the smartmos ic configured as four half-bridge outputs. other ports are also provided including a selectable hvdd pin. an internal voltage regulator is provided on the smartmos ic chip, which provides power to the mcu chip. also included in this device is a lin physical layer, which communicates using a single wire. this enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground. functional pin description see figures 1 , for a graphic representation of the various pins referred to in the following paragraphs. also, see the pin diagram on figures 3 for a depiction of the pin locations on the package. port a i /o pins (pta0:4) these pins are special function, bidirectional i/o port pins that are shared with other func tional modules in the mcu. pta0 : pta4 are shared with the keyboard interrupt pins, kbd0 : kbd4. the pta5/spsck pin is not acce ssible in this device and is internally connected to the spi clock pin of the analog die. the pta6/ ss pin is likewise not accessible. for details refer to the 68hc908ey16 datasheet. port b i/o pins (ptb1, ptb3:7) these pins are special function, bidirectional i/o port pins that are shared with other functional modules in the mcu. all pins are shared with the adc module. the ptb6 : ptb7 pins are also shared with the timer b module. ptb0/ad0 is internally connected to the adout pin of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, v sup , etc. the ptb2/ad2 pin is not accessible in this device. for details refer to the 68hc908ey16 datasheet. port c i/o pins (ptc2:4) these pins are special function, bidirectional i/o port pins that are shared with other functional modules in the mcu. for example, ptc2 : ptc4 are shared with the icg module. ptc0/miso and ptc1/mosi ar e not accessible in this device and are internally conn ected to the miso and mosi spi pins of the analog die. for details refer to the 68hc908ey16 datasheet. port d i /o pins (ptd0:1) ptd1/ tach1 and ptd0/ tach0/bemf are special function, bidirectional i /o port pins that can also be programmed to be timer pins. in step motor applications, the ptd0 pin should be connected to the bemf output of the analog die, to evaluate the bemf signal with a special bemf module of the mcu. ptd1 pin is recommended for use as an output pin for generating the fgen signal (pwm signal), if required by the application. port e i /o pin (pte1) pte1/ rxd and pte0/ txd are special function, bidirectional i/o port pins that can also be programmed to be enhanced serial communication. pte0/txd is internally connected to the txd pin of the analog die. the connection for the receiver must be done externally. external interrupt pin ( irq ) the irq pin is an asynchronous external interrupt pin. this pin contains an internal pull-up resistor that is always activated, even when the irq pin is pulled low. for details refer to the 68hc908ey16 datasheet. external reset pin ( rst ) a logic [0] on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pull-up resistor that is always activated, even when the reset pin is pulled low. for details refer to the 68hc908ey16 datasheet.
analog integrated circuit device data ? 16 freescale semiconductor 908e626 functional description functional pin description current limitation frequency input pin (fgen) input pin for the half-bridge current limitation pwm frequency. this input is not a real pwm input pin; it should just supply the period of th e pwm. the duty cycle will be generated automatically. important the recommended fgen frequency should be in the range of 0.1 khz to 20 khz. back electromagnetic force output pin (bemf) this pin gives the user information about back electromagnetic force (bemf). this feature allows stall detection and coil failures in step motor applications. in order to evaluate this signal the pin must be directly connected to pin ptd0 / tach0 / bemf. reset pin ( rst_a ) rst_a is the bidirectional reset pin of the analog die. it is an open drain with pull-up resist or and must be connected to the rst pin of the mcu. interrupt pin ( irq_a ) irq_a is the interrupt output pin of the analog die indicating errors or wake-up events. it is an open drain with pull-up resistor and must be connected to the irq pin of the mcu. slave select pin ( ss ) this pin is the spi slave select pin for the analog chip. all other spi connections are done internally. ss must be connected to ptb1 or any other logic i /o of the microcontroller. lin bus pin (lin) the lin pin represents the single-wire bus transmitter and receiver. it is suited for autom otive bus systems and is based on the lin bus specification. half-bridge output pins (hb1: hb4) the 908e626 device includes power mosfets configured as four half-bri dge driver outputs. the hb1: hb4 outputs may be configured for step motor drivers, dc motor drivers, or as high side and low side switches. the hb1: hb4 outputs are short-circuit and over- temperature protect ed, and they feature current recopy, current limitation, and bemf ge neration. current limitation and recopy are done on the low side mosfets. power supply pins (vsup1: vsup3) vsup1: vsup3 are device power supply pins. the nominal input voltage is designed for operation from 12 v systems. owing to the low on-resistance and current requirements of the half-bridge driver outputs, multiple vsup pins are provided. all vsup pins must be connected to get full chip functionality. power ground pins (gnd1 and gnd2) gnd1 and gnd2 are device power ground connections. owing to the low on-resistance and current requirements of the half-bridge driver outputs multiple pins are provided. gnd1 and gnd2 pins must be connected to get full chip functionality. switchable v dd output pin (hvdd) the hvdd pin is a switchable v dd output for driving resistive loads requiring a regulated 5.0 v supply; the output is short-circuit protected. + 5.0 v voltage regulator output pin (vdd) the vdd pin is needed to place an external capacitor to stabilize the regulated output voltage. the vdd pin is intended to supply the embedded microcontroller. important the vdd pin should not be used to supply other loads; use the hvdd pin for this purpose. the vdd, evdd, vdda, and vrefh pins must be connected together. voltage regulator ground pin (vss) the vss pin is the ground pin for the connection of all non- power ground connections (microcontroller and sensors). important vss, evss, vssa, and vrefl pins must be connected together. lin transceiver output pin (rxd) this pin is the output of lin transceiver. the pin must be connected to the microcontroller?s enhanced serial communications interface (esci) module (rxd pin). adc reference pins (vrefl and vrefh) vrefl and vrefh are the reference voltage pins for the adc. it is recommended that a high quality ceramic decoupling capacitor be placed between these pins. important vrefh is the high reference supply for the adc and should be tied to the same potential as vdda via separate traces. vrefl is the low reference supply for the adc and should be tied to the same potential as vss via separate traces. for details refer to the 68hc908ey16 datasheet. adc supply pins (vdda and vssa) vdda and vssa are the power supply pins for the analog- to-digital converter (adc). it is recommended that a high quality ceramic decoupling capacitor be placed between these pins. important vdda is the supply for the adc and should be tied to the same potential as evdd via separate traces.
analog integrated circuit device data ? freescale semiconductor 17 908e626 functional description functional pin description vssa is the ground pin for the adc and should be tied to the same potential as evss vi a separate traces. for details refer to the 68hc908ey16 datasheet. mcu power supply pins (evdd and evss) evdd and evss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short- duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu. for details refer to the 68hc908ey16 datasheet. test pin (flsvpp) this pin is for test purposes only. this pin should be either left open (not connected) or connected to gnd. exposed pad pin the exposed pad pin on the bottom side of the package conducts heat from the chip to the pcb board. for thermal performance the pad must be soldered to the pcb board. it is recommended that the pad be connected to the ground potential.
analog integrated circuit device data ? 18 freescale semiconductor 908e626 functional device operation operational modes functional device operation operational modes interrupts the 908e626 has six different interrupt sources as described in the following paragraphs. the interrupts can be disabled or enabled via the spi. after reset all interrupts are automatically disabled. low voltage interrupt the low voltage interrupt (lvi) is related to the external supply voltage, v sup . if this voltage falls below the lvi threshold, it will set the lvi flag. if the low voltage interrupt is enabled, an interrupt will be initiated. with lvi the h-bridges (high side mosfet only) are switched off. all other modules are not influenced by this interrupt. during stop mode the lv i circuitry is disabled. high voltage interrupt the high voltage interrupt (hvi) is related to the external supply voltage, v sup . if this voltage rises above the hvi threshold, it will set the hvi fl ag. if the high voltage interrupt is enabled, an interrupt will be initiated. with hvi the h-bridges (high side mosfet only) are switched off. all other modules are not influenced by this interrupt. during stop mode the hv i circuitry is disabled. high temperature interrupt the high temperature interrupt (hti) is generated by the on-chip temperature sensors. if the chip temperature is above the hti threshold, the hti flag will be set. if the high temperature interrupt is enabled, an interrupt will be initiated. during stop mode the hti circuitry is disabled. autonomous watchdog interrupt (awd) refer to autonomous watchdog (awd) on page 30 . lin interrupt if the linie bit is set, a falling edge on the lin pin will generate an interrupt. during stop mode this interrupt will initiate a system wake-up. over-current interrupt if an over-current condition on a half-bridge or the hvdd output is detected and the ocie bit is set and an interrupt generated. system wake-up system wake-up can be initiat ed by any of four events: ? a falling edge on the lin pin ? a wake-up signal from the awd ? an lvr condition if one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake-up the microcontroller as well as the main voltage regulator (mreg) figures 8 .
analog integrated circuit device data ? freescale semiconductor 19 908e626 functional device operation operational modes figure 8. stop mode / wake-up procedure interrupt flag register (ifr) linf ? lin flag bit this read / write flag is set on t he falling edge at the lin data line. clear linf by writing a logic [1] to linf. reset clears the linf bit. writing a logic [0] to linf has no effect. ? 1 = falling edge on lin data line has occurred. ? 0 = falling edge on lin data line has not occurred since last clear. htf ? high temperature flag bit this read / write flag is set on a high temperature condition. clear htf by writing a logic [1] to htf. if a high temperature condition is still present while writing a logic [1] to htf, the writing has no effect. therefor e, a high temperature interrupt cannot be lost due to inadvertent clearing of htf. reset clears the htf bit. writing a logic [0] to htf has no effect. ? 1 = high temperature condition has occurred. from reset initialize operate spi: gs =1 (mreg off) stop irq interrupt? spi: reason for interrupt operate stop mreg wait for action lin awd hallport assert irq_a start mreg mreg = main voltage regulator mcu die analog die register name and address: ifr - $05 bit 7 6 5 4 3 2 1 bit 0 read 0 0 linf htf lvf hvf ocf 0 write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data ? 20 freescale semiconductor 908e626 functional device operation operational modes ? 0 = high temperature condition has not occurred. lvf ? low voltage flag bit this read / write flag is set on a low voltage condition. clear lvf by writing a logic [1] to lvf. if a low voltage condition is still present while writing a logic [1] to lvf, the writing has no effect. therefore, a low voltage interrupt cannot be lost due to inadvertent clearing of lvf. reset clears the lvf bit. writing a logic [0] to lvf has no effect. ? 1 = low voltage condition has occurred. ? 0 = low voltage condition has not occurred. hvf ? high voltage flag bit this read / write flag is set on a high voltage condition. clear hvf by writing a logic [1] to hvf. if high voltage condition is still present while writing a logic [1] to hvf, the writing has no effect. therefore, a high voltage interrupt cannot be lost due to inadvertent clearing of hvf. reset clears the hvf bit. writing a logic [0] to hvf has no effect. ? 1 = high voltage condition has occurred. ? 0 = high voltage condition has not occurred. ocf ? over-current flag bit this read-only flag is set on an over-current condition. reset clears the ocf bit. to clear this flag, write a logic [1] to the appropriate over-current flag in the sysstat register. see figure 9 , which shows the two signals triggering the ocf. ? 1 = high current condition has occurred. ? 0 = high current condition has not occurred. figure 9. principal implementation for ocf interrupt mask register (imr) linie ? lin line interrupt enable bit this read / write bit enables cpu interrupts by the lin flag, linf. reset clears the linie bit. ? 1 = interrupt requests from linf flag enabled. ? 0 = interrupt requests from linf flag disabled. htie ? high temperature interrupt enable bit this read / write bit enables cpu interrupts by the high temperature flag, htf. re set clears the htie bit. ? 1 = interrupt requests from htf flag enabled. ? 0 = interrupt requests from htf flag disabled. lvie ? low voltage interrupt enable bit this read / write bit enables cpu interrupts by the low voltage flag, lvf. rese t clears the lvie bit. ? 1 = interrupt requests from lvf flag enabled. ? 0 = interrupt requests from lvf flag disabled. hvie ? high voltage interrupt enable bit this read / write bit enables cpu interrupts by the high voltage flag, hvf. reset clears the hvie bit. ? 1 = interrupt requests from hvf flag enabled. ? 0 = interrupt requests from hvf flag disabled. ocie ? over-current interrupt enable bit this read / write bit enables cpu interrupts by the over- current flag, ocf. reset clears the ocie bit. ? 1 = interrupt requests from ocf flag enabled. ? 0 = interrupt requests from ocf flag disabled. reset the 908e626 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. figure 10 depicts the internal reset sources. ocf hvdd_ocf hb_ocf register name and address: imr - $04 bit 7 6 5 4 3 2 1 bit 0 read 0 0 linie htie lvie hvie ocie 0 write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data ? freescale semiconductor 21 908e626 functional device operation operational modes figure 10. internal reset routing reset internal sources autonomous watchdog awd modules generates a reset because of a timeout (watchdog function). high temperature reset to prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. the reset is maskable with bit htre in the reset mask register. after a reset the high temperature reset is disabled. low voltage reset the lvr is related to the internal v dd . in case the voltage falls below a certain threshold, it will pull down the rst_a pin. high voltage reset the hvr is related to the external v sup voltage. in case the voltage is above a certain threshold, it will pull down the rst_a pin. the reset is maskable with bit hvre in the reset mask register. after a reset the high voltage reset is disabled. reset external source external reset pin the microcontroller has the capability of resetting the smartmos device by pulling down the rst pin. reset mask register (rmr) ttest ? high temperature reset test this read / write bit is for test purposes only. it decreases the over-temperature shutdown limit for final test. reset clears the htre bit. ? 1 = low temperature threshold enabled. ? 0 = low temperature threshold disabled. hvre ? high voltage reset enable bit this read / write bit enables resets on high voltage conditions. reset clears the hvre bit. ? 1 = high voltage reset enabled. ? 0 = high voltage reset disabled. htre ? high temperature reset enable bit this read / write bit enables resets on high temperature conditions. reset clears the htre bit. ? 1 = high temperature reset enabled. ? 0 = high temperature reset disabled. htre flag hvre flag awdre flag awd reset sensor high-voltage reset sensor high-temperature reset sensor mono flop low-voltage reset vdd rst_a spi registers register name and address: rmr - $06 bit 7 6 5 4 3 2 1 bit 0 read ttest 0 0 0 0 0 hvre htre write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data ? 22 freescale semiconductor 908e626 functional device operation operational modes serial peripheral interface the serial peripheral interface (spi) creates the communication link between the microcontroller and the 908e626. the interface consists of four pins (see figure 11 ): ? ss ? slave select ?mosi ? master-out slave-in ?miso ? master-in slave-out ? spsck ? serial clock (maximum frequency 4.0 mhz) a complete data transfer via the spi consists of 2 bytes. the master sends address and data, slave system status, and data of the selected address. figure 11. spi protocol during the inactive phase of ss , the new data transfer is prepared. the falling edge on the ss line indicates the start of a new data transfer and put s miso in the low-impedance mode. the first valid data are moved to miso with the rising edge of spsck. the miso output changes data on a rising edge of spsck. the mosi input is sa mpled on a falling edge of spsck. the data transfer is only valid if exactly 16 sample clock edges are present in the active phase of ss . after a write operation, the tran smitted data is latched into the register by the rising edge of ss . register read data is internally latched into the spi at the time when the parity bit is transferred. ss high forces miso to high-impedance. master address byte a4 : a0 contains the address of the desired register. r / w contains information about a read or a write operation. ?if r/ w = 1, the second byte of master contains no valid information, slave just transmits back register data. ?if r/ w = 0, the master sends da ta to be written in the second byte, slave sends concurrently contents of selected register prior to wr ite operation, write data is latched in the smartmos register on rising edge of ss . parity p the parity bit is equal to ?0? if the number of 1 bits is an even number contained within r/ w , a4 : a0. if the number of 1 bits is odd, p equals ?1?. for example, if r/ w = 1, a4 : a0 = 00001, then p equals ?0.? the parity bit is only evalua ted during a write operation. bit x not used. master data byte contains data to be written or no valid data during a read operation. s7 s6 s5 s4 s3 s2 s1 s0 r/w a4 a3 a2 a1 a0 p x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 system status register read/write, address, parity data (register write) data (register read) rising edge of spsck change miso/mosi output falling edge of spsck sample miso/mosi input slave latch register address slave latch data ss mosi miso spsck
analog integrated circuit device data ? freescale semiconductor 23 908e626 functional device operation operational modes slave status byte contains the contents of the s ystem status register ($0c) independent of whether it is a write or read operation or which register was selected. slave data byte contains the contents of sele cted register. during a write operation it includes the regist er content prior to a write operation. spi register overview table summarizes the spi register addresses and the bit names of each register. analog die i / os lin physical layer the lin bus pin provides a physical layer for single-wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer specification. the lin driver is a low side mosfet with internal current limitation and thermal shutdown. an internal pull-up resistor with a serial diode structure is integrated, so no external pull- up components are required for the application in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominant is controlled. the symmetry between both slew rate controls is guaranteed. the lin pin offers high suscept ibility immunity level from external disturbance, guar anteeing communication during external disturbance. the lin transmitter circuitry is enabled by setting the pson bit in the system control register (sysctl). if the transmitter works in the current limitation region, the lincl bit in the system status regi ster (sysstat) is set. due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. txd pin the txd pin is the mcu interfac e to control t he state of the lin transmitter (see figure , page 2 ). when txd is low, lin output is low (dominant state) . when txd is high, the lin output mosfet is turned off. the txd pin has an internal pull-up current source in order to set the lin bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. table 6. list of registers addr register name r/w bit 76543210 $01 h-bridge output (hbout) r hb4_h hb4_l hb3_h hb3_l hb2_h hb2_l hb1_h hb1_l w $02 h-bridge control (hbctl) r ofc_en csa 000 cls2 cls1 cls0 w $03 system control (sysctl) r pson srs1 srs0 0000 0 w gs $04 interrupt mask (imr) r 0 0 linie htie lvie hvie ocie 0 w $05 interrupt flag (ifr) r 0 0 linf htf lvf hvf ocf 0 w $06 reset mask (rmr) r ttest 00000 hvre htre w $07 analog multiplexer configuration (admux) r0000 ss3 ss2 ss1 ss0 w $08 reserved r00000 000 w $09 reserved r00000000 w $0a awd control (awdctl) r000 awdre awdie 0 awdf awdr w awdrst $0b power output (pout) r0 0 0000hvddon0 w $0c system status (sysstat) r 0 lincl hvdd_oc f 0 lvf hvf hb_ocf htf w
analog integrated circuit device data ? 24 freescale semiconductor 908e626 functional device operation operational modes rxd pin the rxd transceiver pin is the mcu interface, which reports the state of the lin bus voltage. lin high (recessive state) is reported by a high level on rxd, lin low (dominant state) by a low level on rxd. stop mode/wake-up feature during stop mode operation the transmitter of the physical layer is disabled. the receiver pin is still active and able to detect wake-up events on the lin bus line.if lin interrupt is enabled (linie bit in the interrupt mask register is set), a falling edge on the lin line causes an interrupt. this interrupt switches on the main voltage regulator and generates a system wake-up. analog multiplexer /adout pin the adout pin is the analog output interface to the adc of the mcu (see figure , page 2 ). an analog multiplexer is used to read six internal diagnostic analog voltages. current recopy the analog multiplexer is connected to the four low side current sense circuits of the half-bridges. these sense circuits offer a voltage proportional to the current through the low side mosfet. high or low resolution is selectable: 5.0 v / 2.5 a or 5.0 v / 500 ma, respectively. (refer to half-bridge current recopy on page 27 .) temperature sensor the 908e626 includes an on-chip temperature sensor. this sensor offers a voltage that is proportional to the actual chip junction temperature. v sup prescaler the v sup prescaler permits the reading or measurement of the external supply voltage. the output of this voltage is v sup / ratio vsup . the different internal diagnostic analog voltages can be selected with the admux register. analog multiplexer config uration register (admux) ss3, ss2, ss1, and ss0 ? a / d input select bits these read / write bits select the input to the adc in the microcontroller according to table , page 24 . reset clears ss3, ss2, ss1, and ss0 bits. power output register (pout) hvddon ? hvdd on bit this read/write bit enables hvdd output. reset clears the hvddon bit. ? 1 = hvdd enabled. ? 0 = hvdd disabled. register name and address: admux - $07 bit 7 6 5 4 3 2 1 bit 0 read 0 0 0 0 ss3 ss2 ss1 ss0 write reset 0 0 0 0 0 0 0 0 table 7. analog multiplexer configuration register ss3 ss2 ss1 ss0 channel 0000 current recopy hb1 0001 current recopy hb2 0010 current recopy hb3 0011 current recopy hb4 0100 v sup prescaler 0101 temperature sensor 0110 not used 0111 1000 1001 1010 1011 1100 1101 1110 1111 register name and address: p out - $0b bit 7 6 5 4 3 2 1 bit 0 read 0 0 0 (17) 0 (17) 0 (17) 0 (17) hvdd on 0 (17) write reset 0 0 0 0 0 0 0 0 notes 17. this bit must always be set to 0.
analog integrated circuit device data ? freescale semiconductor 25 908e626 functional device operation operational modes half-bridges outputs hb1 : hb4 provide four low resistive half-bridge output stages. the half-bridges can be used in h-bridge, high side, or low side configurations. reset clears all bits in the h-bridge output register (hbout) owing to the fact that all half-bridge outputs are switched off. hb1: hb4 output features: ? short-circuit (over-current) protection on high side and low side mosfets. ? current recopy feat ure (low side mosfet). ? over-temperature protection. ? over-voltage and under-voltage protection. ? current limitation feature (low side mosfet). figure 12. half-bridge push-pull output driver half-bridge control each output mosfet can be controlled individually. the general enable of the circuitry is done by setting pson in the system control register (sysctl). hbx_l and hbx_h form one half-bridge. it is not possi ble to switch on both mosfets in one half-bridge at the same time. if both bi ts are set, the high side mosfet has a higher priority. to avoid both mosfets (high side and low side) of one half-bridge being on at the same time, a break-before-make circuit exists. switching the high side mosfet on is inhibited as long as the potential between gate and v ss is not below a certain threshold. switching the low side mosfet on is blocked as long as the potential between gate and source of the high side mosfet did not fall below a certain threshold. half-bridge output register (hbout) hbx_l ? low side on / off bits these read / write bits turn on the low side mosfets. reset clears the hbx_l bits. ? 1 = low side mosfet turned on for half-bridge output x. ? 0 = low side mosfet turned off for half-bridge output x. high side driver charge pump, over-temperature protection, over-current protection low side driver current recopy, current limitation, over-current protection control on/off status on/off status current limit hbx vsup gnd bemf register name and address: hbout - $01 bit 7 6 5 4 3 2 1 bit 0 read hb4 _ h hb4 _ l hb3 _ h hb3 _ l hb2 _ h hb2 _ l hb1 _ h hb1 _ l write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data ? 26 freescale semiconductor 908e626 functional device operation operational modes hbx_h ? high side on/off bits these read / write bits turn on the high side mosfets. reset clears the hbx_h bits. ? 1 = high side mosfet turned on for half-bridge output x. ? 0 = high side mosfet turned on for half-bridge output x. half-bridge current limitation each low side mosfet offers a current limit or constant current feature. this features is realized by a pulse width modulation on the low side mosfet. the pulse width modulation on the outputs is controlled by the fgen input and the load characteristics. the fgen input provides the pwm frequency, wher eas the duty cycle is controlled by the load characteristics. the recommended frequency range for the fgen and the pwm is 0.1 khz to 20 khz. functionality each low side mosfet switches off if a current above the selected current limit was detec ted. the 908e626 offers five different current limits (refer to table , for current limit values). the low side mosfet switches on again if a rising edge on the fgen input was detected ( figure 13 ). figure 13. half-bri dge current limitation coil current half-bridge low side output fgen input (mcu pwm signal) minimum 50 s h-bridge low side mosfet will be switched off if select current limit is reached. h-bridge low side mosfet will be tur ned on with each rising edge of the fgen input. t (s) t (s) t (s)
analog integrated circuit device data ? freescale semiconductor 27 908e626 functional device operation operational modes offset chopping if bit ofc_en in the h-bridge control register (hbctl) is set, hb1 and hb2 will continue to switch on the low side mosfets with the rising edge of the fgen signal and hb3 and hb4 will switch on the low side mosfets with the falling edge on the fgen input. in step motor applications, this feature allows the reduction of emi due to a reduction of the di/dt ( figure 14 ). figure 14. offset chopping for step motor control half-bridge current recopy each low side mosfet has an additional sense output to allow a current recopy feature. this sense source is internally connected to a shunt resistor. the drop voltage is amplified and switched to the analog multiplexer. the factor for the current sense amplification can be selected via bit csa in the system control register. ? csa = 1: low resolution selected (500 ma measurement range). ? csa = 0: high resolution selected (2.5 a measurement range). half-bridge bemf generation the bemf output is set to ?1? if a recirculation current is detected in any half-bridge. this recirculation current flows via the two freewheeling diodes of the power mosfets. the bemf circuitry detects that and generates a high on the bemf output as long as a recirc ulation current is detected. this signal provides a flexible and reliable detection of stall in step motor applications. for this the bemf circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. in addition the signal can be used for open load detection (absence of this signal) (see figure 15 ). coil2 current coil1 current current in vsup line fgen input (mcu pwm signal) coil1 ?.. coil2 ?.. hb1 hb2 hb3 hb4
analog integrated circuit device data ? 28 freescale semiconductor 908e626 functional device operation operational modes figure 15. bemf signal generation half-bridge over-temperature protection the half-bridge outputs pr ovide an over-temperature prewarning with the htf in the interrupt flag register (ifr). in order to protect the output s against over-temperature, the high temperature reset must be enabled. if this value is reached, the part generates a reset and disables all power outputs. half-bridge over-current protection the half-bridges are protected against short to gnd, short to vsup, and load shorts. in the event an over-current on the high side is detected, the high side mosfets on all hb high side mosfets are switched off autom atically. in the event an over-current on the low side is detected, all hb low side mosfets are switched off automatically. in both cases, the over-current status flag hb_ocf in the system status register (sysstat) is set. the over-current status flag is cleared (and the outputs re- enabled) by writing a logic [1] to the hb_ocf flag in the system status register or by reset. half-bridge over-voltage / under- voltage the half-bridge outputs ar e protected against under- voltage and over-voltage conditions. this protection is done by the low and high voltage interrupt circuitry. if one of these flags (lvf, hvf) is set, t he outputs are automatically disabled. the over-voltage / under-voltage status flags are cleared (and the outputs re-enabled) by writing a logic [1] to the lvf / hvf flags in the interrupt flag register or by reset. clearing this flag is useless as long as a high or low voltage condition is present. half-bridge control register (hbctl) ofc_en ? h-bridge offset chopping enable bit this read / write bit enables offset chopping. reset clears the ofc_en bit. ? 1 = offset chopping enabled. ? 0 = offset chopping disabled. coil current voltage on 1 1 bemf signal register name and address: hbctl - $02 bit 7 6 5 4 3 2 1 bit 0 read ofc_en csa 0 0 0 cls2 cls1 cls0 write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data ? freescale semiconductor 29 908e626 functional device operation operational modes csa ? h-bridges current sense amplification select bit this read / write bit selects the curr ent sense amplification of the h-bridges. reset clears the csa bit. ? 1 = current sense amplification set for measuring 0.5 a. ? 0 = current sense amplification set for measuring 2.5 a. cls2 : cls0 ? h-bridge current limitation selection bits these read / write bits select the current limitation value according to table . reset clears the cls2 : cls0 bits. switchable vdd outputs the hvdd pin is a switchable vdd output pin. it can be used for driving external circuitry that requires a v dd voltage. the output is enabled with bit pson in the system control register and can be switched on / off with bit hvddon in the power output register. low or high voltage conditions (lvi / hvi) have no influence on this circuitry. hvdd over-temperature protection over-temperature protection is enabled if the high temperature reset is enabled. hvdd over-current protection the hvdd output is protected against over-current. in the event the over-current limit is or was reached, the output automatically switches off and the hvdd over-current flag in the system status register is set. system control register (sysctl) pson ? power stages on bit this read / write bit enables the power stages (half-bridges, lin transmitter and hvdd out put). reset clears the pson bit. ? 1 = power stages enabled. ? 0 = power stages disabled. srs0 : srs1 ? lin slew rate selection bits these read / write bits enable the user to select the appropriate lin slew rate for different baud rate configurations as shown in table . the high speed slew rates are used, for example, for programming via the lin and are not intended for use in the application. go to stop mode bit (gs) this write-only bit instructs the 908e626 to power down and go into stop mode. rese t or cpu interrupt requests clear the gs bit. ? 1 = power down and go into stop mode ? 0 = not in stop mode system status register (sysstat) lincl ? lin current limitation bit this read-only bit is set if t he lin transmitter operates in current limitation region. due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. ? 1 = transmitter operating in current limitation region. ? 0 = transmitter not operating in current limitation region. hvdd_ocf ? hvdd output over-current flag bit this read / write flag is set on an ov er-current condition at the hvdd pin. clear hvdd_ocf and enable the output by writing a logic [1] to the hvdd_ocf flag. reset clears the table 8. h-bridge current limitation value selection bits cls2 cls1 cls0 current limit 000 no limit 001 010 011 55 ma (typ) 100 260 ma (typ) 101 370 ma (typ) 110 550 ma (typ) 111 740 ma (typ) register name and address: sysctl - $03 bit 7 6 5 4 3 2 1 bit 0 read pson srs1 srs0 0 0 0 0 0 write gs reset 0 0 0 0000 0 table 9. lin slew rate selection bits srs1 srs0 lin slew rate 0 0 initial slew rate (20 kbaud) 0 1 slow slew rate (10 kbaud) 1 0 high speed ii (8 x) 1 1 high speed i (4 x) register name and address: sysstat - $0c bit 7 6 5 4 3 2 1 bit 0 read 0 lincl hvdd _ocf 0 lvf hvf hb_ ocf htf write reset 00000000
analog integrated circuit device data ? 30 freescale semiconductor 908e626 functional device operation operational modes hvdd_ocf bit. writing a logic [0] to hvdd_ocf has no effect. ? 1 = over-current condition on hvdd has occurred. ? 0 = no over-current condition on hvdd has occurred. lvf ? low voltage bit this read only bit is a copy of the lvf bit in the interrupt flag register. ? 1 = low voltage condition has occurred. ? 0 = no low voltage condition has occurred. hvf ? high voltage sensor bit this read-only bit is a copy of the hvf bit in the interrupt flag register. ? 1 = high voltage condition has occurred. ? 0 = no high voltage condition has occurred. hb_ocf ? h-bridge over-current flag bit this read / write flag is set on an over-current condition at the h-bridges. clear hb_ocf and enable the h-bridge driver by writing a logic [1] to hb_ocf. re set clears the hb_ocf bit. writing a logic [0] to hb_ocf has no effect. ? 1 = over-current condition on h-bridges has occurred. ? 0 = no over-current condition on h-bridges has occurred. htf ? over-temperature status bit this read-only bit is a copy of the htf bit in the interrupt flag register. ? 1 = over-temperature condition has occurred. ? 0 = no over-temperature condition has occurred. autonomous watchdog (awd) the autonomous watchdog module consists of three functions: ? watchdog function for the cpu in run mode ? periodic interrupt function in stop mode the autonomous watchdog module allows to protect the cpu against code runaways. the awd is enabled if awdie, awdre in the awdctl register is set. if this bit is cleared, the awd oscillator is disabled and the watchdog switched off. watchdog the watchdog function is only available in run mode. on setting the awdre bit, watchdog functionality in run mode is activated. once this function is enabled, it is not possible to disable it via software. if the timer reaches end value and awdre is set, a system reset is initiated. operations of the watchdog function cease in stop mode. norma l operation will be continued when the system is back to run mode. to prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. this is done by a write to the awdrst bit in the awdctl register. periodic interrupt periodic interrupt is only av ailable in stop mode. it is enabled by setting the awdie bit in the awdctl register. if awdie is set, the awd wake s up the system after a fixed period of time. this time period can be selected with bit awdr in the awdctl register. autonomous watchdog control register (awdctl) awdrst ? autonomous watchdog reset bit this write-only bit resets the autonomous watchdog timeout period. awdrst always reads 0. reset clears awdrst bit. ? 1 = reset awd and restart timeout period. ? 0 = no effect. awdre ? autonomous watchdog reset enable bit this read / write bit enables resets on awd timeouts. a reset on the rst_a is asserted when the autonomous watchdog has reached the ti meout and the autonomous watchdog is enabled. awdre is one-time setable (write once) after each reset. rese t clears the awdre bit. ? 1 = autonomous watchdog enabled. ? 0 = autonomous watchdog disabled. autonomous watchdog inte rrupt enable bit (awdie) this read/write bit enables cpu interrupts by the autonomous watchdog timeout flag, awfd. irq_a is only asserted when the device is in stop mode. reset clears the awdie bit. ? 1 = cpu interrupt requests from awdf enabled ? 0 = cpu interrupt requests from awdf disabled awdr ? autonomous watchdog rate bit this read / write bit selects the clock rate of the autonomous watchdog. reset clears the awdr bit. ? 1 = fast rate selected (10 ms). ? 0 = slow rate selected (20 ms). register name and address: awdctl - $0a bit 7 6 5 4 3 2 1 bit 0 read 00 0 awdre awdie 0 (18) 0 awdr write awdrst reset 00 0 0 0 00 0 notes 18. this bit must always be set to 0.
analog integrated circuit device data ? freescale semiconductor 31 908e626 functional device operation factory trimming and calibration voltage regulator the 908e626 chip contains a low power, low drop voltage regulator to provide internal power and external power for the mcu. the v dd regulator accepts a unregulated input supply and provides a regulated v dd supply to all digital sections of the device. the output of the re gulator is also connected to the vdd pin to provide the 5.0 v to the microcontroller. note: under loss of power conditions, the discharge of the v dd capacitor may occur relatively slow. based on the selected external components and external v dd load, additional external load may be required guarantee the mcu por threshold being reached before the next power up. run mode during run mode, the main voltage regulator is on. it provides a regulated supply to all digital sections. stop mode during stop mode the stop mode regulator supplies a regulated output voltage. th e stop mode regulator has a very limited output current cap ability. the output voltage will be lower than the output volt age of the main voltage regulator. factory trimming and calibration to enhance the ease-of-use of the 908e626, various parameters (e.g. icg trim value) are stored in the flash memory of the device. the following flash memory locations are reserved for this purpose and might have a value different from the empty (0xff) state: ? 0xfd80: 0xfddf trim and calibration values ? 0xfffe : 0xffff reset vector in the event the application uses these parameters, one has to take care not to erase or override these values. if these parameters are not used, these flash locations can be erased and otherwise used. trim values below the usage of the trim values located in the flash memory is explained internal clock genera tor (icg) trim value the internal clock generator (icg) module is used to create a stable clock source for the microcontroller without using any external components. the untrimmed frequency of the low frequency base clock (ibase), will vary as much as 25%, due to process, temperature, and voltage dependencies. to compensate this dependencies a icg trim values is located at address $fdc2. after trimming the icg is a range of typ. 2% (3% max.) at nominal conditions (filtered (100 nf) and stabilized (4.7 ? f) v dd = 5.0 v, t ambient ~25 c) and will vary over temperature and voltage (vdd) as indicated in the 68hc908ey16 datasheet. to trim the icg this values has to be copied to the icg trim register icgtr at address $38 of the mcu. important the value has to be copied after every reset.
analog integrated circuit device data ? 32 freescale semiconductor 908e626 typical applications typical applications development support as the 908e626 has the mc68hc908ey16 mcu embedded, typically all the development tools available for the mcu also apply for this device. however, due to the fact of the additional analog die circuitry and the nominal +12 v supply voltage some additional items have to be considered: ? nominal 12 v rather than 5.0 v or 3.0 v supply ? high voltage v tst might be applied not only to irq pin, but also the irq_a pin for a detailed information on the mcu related development support, see t he mc68hc908ey16 datasheet - section, development support. the programming is principally possible at two stages in the manufacturing process - first on chip level, before the ic is soldered onto a pcb board, and second, after the ic is soldered onto the pc board. chip level programming at the chip level, the easiest way is to only power the mcu with +5.0 v (see figure 16 ), and not provide the analog chip with vsup. in this setup, all the analog pins should be left open (e.g. vsup[1:3]), and in terconnections between the mcu and the analog die have to be separated (e.g. irq - irq_a ). this mode is well described in the mc68hc908ey16 datasheet - section, development support. figure 16. normal monito r mode circuit (mcu only) it is also possible to supply the whole system with v sup (12 v) instead as described in figure 17 . pcb level programming if the ic is soldered onto the pc board, it is typically not possible to separately power the mcu with +5.0 v. the whole system has to be powered up providing v sup (see figure 17 ). mm908e626 rst_a rst irq_a irq vsup[1:3] gnd[1:2] ptc4/osc1 ptb3/ad3 ptb4/ad4 pta0/kbd0 pta1/kbd1 max232 10k rs232 db-9 1 3 c1+ c1- 4 5 c2+ c2- 7 8 2 3 5 v cc gnd 16 15 2 v+ v- 6 1f + 1f + + 1f 1f + + 1f 2 1 3 65 4 74hc125 74hc125 9.8304mhz clock +5v +5v data clk +5v 10k 10k 10k v tst 10 9 t2 out r2 in t2 in r2 out evdd vdd vss 4.7f 100nf +5v vrefl vdda evss vrefh vssa
analog integrated circuit device data ? freescale semiconductor 33 908e626 typical applications figure 17. normal monitor mode circuit table 10 summarizes the possible configurations and the necessary setups. mm908e626 rst_a rst irq_a irq vdd vss vsup[1:3] gnd[1:2] ptc4/osc1 ptb3/ad3 ptb4/ad4 pta0/kbd0 pta1/kbd1 max232 10k rs232 db-9 1 3 c1+ c1- 4 5 c2+ c2- 7 8 2 3 5 v cc gnd 16 15 2 v+ v- 6 1f + 1f + + 1f 1f + + 1f 2 1 3 65 4 74hc125 74hc125 9.8304mhz clock v dd v dd data clk v dd 10k 10k 10k v dd v tst v sup 47f + 100nf 10 9 t2 out r2 in t2 in r2 out evdd 4.7f 100nf vrefl vdda evss vrefh vssa table 10. monitor mode signal requirements and options mode irq rst reset vector serial communication mode selection icg cop normal request timeout communication speed pta0 pta1 ptb3 ptb4 external clock bus frequency baud rate normal monitor v tst v dd x 1 0 0 1 off disabled disabled 9.8304 mhz 2.4576 mhz 9600 forced monitor v dd v dd $ffff (blank) 1 0 x x off disabled disabled 9.8304 mhz 2.4576 mhz 9600 gnd on disabled disabled ? nominal 1.6 mhz nominal 6300 user v dd v dd not $ffff (not blank) x x x x on enabled enabled ? nominal 1.6 mhz nominal 6300 notes 19. pta0 must have a pull-up resistor to v dd in monitor mode 20. external clock is a 4.9152 mhz, 9.8304 mhz or 19.6608 mhz canned oscillator on ocs1 21. communication speed with external clock is depending on external clock value. baud rate is bus frequency / 256 22. x = don?t care 23. v tst is a high voltage v dd + 3.5 v ?? v tst ? v dd + 4.5 v
analog integrated circuit device data ? 34 freescale semiconductor 908e626 typical applications emc/emi recommendations this paragraph gives some device specific recommendations to improve emc/emi performance. further generic design recommendations can be found on the freescale web site, www.freescale.com. vsup pins (vsup1:vsup3) its recommended to place a high quality ceramic decoupling capacitor close to the vsup pins to improve emc/emi behavior. lin pin for dpi (direct power injection) and esd (electrostatic discharge) its recommended to place a high quality ceramic decoupling capacitor near the lin pin. an additional varistor will further increase the immunity against esd. a ferrite in the lin line will suppress some of the noise induced. voltage regulator output pins (vdd and agnd) use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. mcu digital supply pins (evdd and evss) fast signal transitions on mcu pins place high, short duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu. it is recommended that a high quality ceramic decoupling capacitor be placed between these pins. mcu analog supply pins (vrefh, vdda, vrefl, and vssa) to avoid noise on the analog su pply pins its important to take special care on the layout. the mcu digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. figure 18 and figure 19 show the recommendations on schematics and layout level and table 11 indicates recommended external components and layout considerations. figure 18. emc/emi recommendations mm908e625 vrefl vdda evdd vdd evss vss vsup1 gnd1 v sup + vrefh vssa vsup2 lin lin c1 c2 d1 c3 c4 c5 l1 v1 vsup3 gnd2
analog integrated circuit device data ? freescale semiconductor 35 908e626 typical applications figure 19. pcb layout recommendations . table 11. component value recommendation component recommended value (24) comments / signal routing c1 bulk capacitor c2 100 nf, smd ceramic, low esr close (<5.0 mm) to the vsup1, vsup2 pins with good ground return c3 100 nf, smd ceramic, low esr close (<3.0 mm) to the digital s upply pins (evdd, evss) with good ground return. the positive analog (vrefh, vdda) and the digital (evdd) supply should be connected right at the c3. c4 4,7 ? f, smd ceramic, low esr bulk capacitor c5 180 pf, smd ceramic, low esr close (<5.0 mm) to lin pin. total capacitance on lin has to be below 220 pf. (c total = c lin-pin + c5 + c varistor ~ 10 pf + 180 pf + 15 pf) v1 (25) varistor type tdk avr-m1608c270mbaab optional (close to lin connector) l1 (25) smd ferrite bead type tdk mmz2012y202b optional, (close to lin connector) notes 24. freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit d rawings or tables. while freescale offers component recommendations in this configuration, it is the cust omer?s responsibility to valid ate their application. 25. components are recommended to improve emc and esd performance. 1 2 4 3 5 6 7 8 9 11 10 12 13 14 15 16 18 17 19 20 21 22 23 25 24 26 27 54 53 51 52 50 49 48 47 46 44 45 43 42 41 40 39 37 38 36 35 34 33 32 30 31 29 28 908e626 lin vbat gnd1 gnd2 vsup2 vsup3 gnd c1 l1 evdd evss vdda vssa vdd vss vsup1 lin vrefh vrefl nc nc nc nc c5 c4 c3 v1 c2
analog integrated circuit device data ? 36 freescale semiconductor 908e626 packaging packaging dimensions packaging packaging dimensions important: for the most current revi sion of the package, visit www.freescale.com and perform a keyword search on 98arl10519d. dimensions shown are provided for reference only. ek suffix (pb-free) 54-pin 98arl10519d issue d
analog integrated circuit device data ? freescale semiconductor 37 908e626 packaging packaging dimensions ek suffix (pb-free) 54-pin 98arl10519d issue d
analog integrated circuit device data ? 38 freescale semiconductor 908e626 packaging packaging dimensions ek suffix (pb-free) 54-pin 98arl10519d issue d
analog integrated circuit device data ? freescale semiconductor 39 908e626 additional documentation thermal addendum (rev 1.0) additional documentation thermal addendum (rev 1.0) introduction this thermal addendum ia provided as a supplement to the mm908e626 technical data sheet. the addendum provides thermal performance information that may be critical in the design and devel opment of system a pplications. all electrical, application and packaging information is provided in the data sheet. package and thermal considerations this mm908e626 is a dual die package. there are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r ? ja mn . for m , n = 1, r ? ja11 is the thermal resistance from junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m = 1, n = 2, r ? ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r ? j21 and r ? j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standardized environment. this metho dology is not meant to and will not predict the performance of a package in an application-specific environm ent. stated values were obtained by m easurement and simulation according to the standards listed below. standards figure 20. thermal land pattern for direct thermal attachment per jedec jesd51-5thermal test board 54-pin soicw-ep 908e626 98arl10519d 54-pin soicw-ep note for package dimensions, refer to 98arl10519d. t j1 t j2 = r ? ja11 r ? ja21 r ? ja12 r ? ja22 . p 1 p 2 table 12. thermal pe rformance comparison thermal resistance 1 = power chip, 2 = logic chip [ ? c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ? ja mn (1)(2) 23 20 24 r ? jb mn (2)(3) 9.0 6.0 10 r ? ja mn (1)(4) 52 47 52 r ? jc mn (5) 1.0 0 2.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7and ? jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad, ?infinite? heat sink attached to exposed pad. 1.0 1.0 0.2 0.2 soldermast openings thermal vias connected to top buried plane 54 terminal soic-ep 0.65 mm pitch 17.9 mm x 7.5 mm body 10.3 mm x 5.1 mm exposed pad * all measurements are in millimeters
analog integrated circuit device data ? 40 freescale semiconductor 908e626 additional documentation thermal addendum (rev 1.0) figure 21. thermal test board device on thermal test board r ? ja ? is the thermal resistance between die junction and ambient air. r ? jsmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. 908e626 pin connections 54-pin soicw-ep 0.65 mm pitch 17.9 mm x 7.5 mm body pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 vrefh vdda evdd evss vssa vrefl pte1/rxd rxd vss nc vdd nc nc nc hvdd nc hb4 vsup3 gnd2 hb3 nc flsvpp ptb7/ad7/tbch1 ptb6/ad6/tbch0 ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 irq rst ptb1/ad1 ptd0/tach0/bemf ptd1/tach1 nc fgen bemf rst_a irq_a ss lin nc nc hb1 vsup1 gnd1 hb2 vsup2 1 11 12 13 14 15 16 17 18 19 20 9 10 21 22 23 24 25 26 27 6 7 8 4 5 2 3 54 44 43 42 41 40 39 38 37 36 35 46 45 34 33 32 31 30 29 28 49 48 47 51 50 53 52 exposed pad a 10.3 mm x 5.1 mm exposed pad a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 13. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( ? c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 r ? ja mn 053 48 53 300 39 34 38 600 35 30 34 r ? js mn 021 16 20 300 15 11 15 600 14 9.0 13
analog integrated circuit device data ? freescale semiconductor 41 908e626 additional documentation thermal addendum (rev 1.0) figure 22. device on thermal test board r ? ja figure 23. transient thermal resistance r ? ja (1.0 w step response) device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 heat spreading area a [mm2] thermal resistance [oc/w] 0 300 600 r ? ja11 r ? ja22 r ? ja12 =r ? ja21 x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] r ? ja11 r ? ja22 r ? ja12 =r ? ja21 x
analog integrated circuit device data ? 42 freescale semiconductor 908e626 revision history revision history revision date description of changes 4.0 9/2008 ? implemented revision history page ? minor corrections throughout the document ? updated to current freescale format and style ? added mm908e626avek to the ordering information ? corrected package drawing designation ? added stop mode 5.0 7/2009 ? corrected several non-technical cross-references. 6.0 9/2011 ? corrected text for autonomous watchdog interrupt. page 17. ? corrected part number in go to stop mode bit. page 30. ? removed footnotes in register table for sysctl and awdctl. ? corrected figure 4 lin timing description. ? updated freescale form and style ? added MM908E626AVPEK to the ordering information. ? removed the dwb package type. ? added rohs image to page 1 and rohs statement to back page. ? changed peak package reflo temperat ure during reflow description ? added note (8) 7.0 04/2012 ? added MM908E626AVPEK to the ordering information ? removed 908e626avek/ r2 from the ordering information ? updated freescale form and style 8.0 4/2012 ? corrected figure 4, lin timing description , replacing v lin with v sup
document number: mm908e626 rev. 8.0 4/2012 information in this document is provide d solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s tech nical experts. freesc ale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net /v2/webservices/freescale/ docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, po werquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semico nductor, inc., reg. u.s. pat. & tm. off. ? airfast, beekit, beestack, coldfire+, co renet, flexis, magniv, mxc, platform in a package, processor expert, qoriq qonverge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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